1. Field of the Invention
This invention relates generally to semiconductor memory devices performing data storage based on whether current pull-in is present or absent or alternatively whether it is large or small in intensity. More particularly but not exclusively, the invention relates to improvements in sense amplifier circuit schemes for performing data sensing by comparison of a voltage potential on a data line to that on a reference data line.
2. Description of Related Art
Currently available semiconductor memory device include non-volatile data storable memory devices such as electrically erasable and programmable read-only memory (EEPROM) chips with nonvolatile data storing functionalities while offering electrical reprogramming capabilities. EEPROMs in turn include ones of the type erasing a plurality of memory cells at a time, which are called “flash” memories among those skilled in the art. In the flash memories, data is stored in a memory cell as a threshold voltage change accomplished by injection or extraction electrical charge carriers at its floating gate. A logical value of the stored data is determinable by detecting whether cell current pull-in is present or absent or, alternatively, whether it is large or small in intensity. To do this, flash memories are typically designed to employ sense amplifier circuit of the current-sensing type. Most current-sensing type sense amplifier circuits make use of schemes for reading data through comparison of a voltage potential on a data line to a predetermined reference voltage on a reference data line.
One prior known sense amplifier circuit using such schemes is shown in FIG. 32. This circuit is formed of a differential amplifier 101 for use as a “core” circuit thereof. The differential amplifier 101 has input terminals, one of which is connected to a sense line SN and the other of which is to a reference sense line RSN. Sense line SN is coupled to a current-source load 102 whereas reference sense line RSN is to its own current-source load 201. Sense line SN and reference sense line RSN are connected through separation (clamping) circuits 105, 202 to a data line DL and a reference data line RDL, respectively.
Data is read out of a memory cell MC onto the data line DL. More practically in the case of large-capacity flash memory chips, the data of memory cell MC is read through a multiple-stage selection route in a way which follows: the data is first read onto a local bit line BL and is then transferred via a first column gate 103 to a main bit line MBL and further sent to the data line DL through a second column gate 104. The reference data line RDL is operatively associated with a current source 203 connected thereto. Current source 203 has a current value which is set midway between a cell current expected to flow when the memory cell MC's data is a logic “0” and a cell current flowing when the data is a logic “1.” Connected to current source 203 is a dummy data line capacitor CR which is for establishment of a capacitive balance relative to data line DL.
An ensemble of the current-source load 201 on the reference sense line RSN side and the separator circuit 202 plus the reference sense line RSN makes up a reference voltage generation circuit 200 that is operable to generate a reference voltage for detection of a voltage of cell data being sent to the sense line SN.
The data line DL has a large load. Thus, it is required for high-speed sensing operations to perform data detection while suppressing the amplitude or “swing width” of a voltage on such data line DL. To this end, a clamping circuit 105 is provided between data line DL and sense line SN for suppressing the voltage swing width on data line DL. Using this clamp circuit 105 enables separation or isolation of data line DL from sense line SN, causing sense line SN to decrease in capacitance.
Reportedly, the voltage swing width of data line DL when reading data bits of a logic “0” and logic “1” and that of sense line SN in 0-read and 1-read events exhibit a relationship shown in FIG. 33. In this graph a voltage swing width on sense line SN between 0- and 1-read is represented by ΔVSN whereas that of data line DL is given as ΔVDL. Customarily these widths ΔVSN, ΔVDL are specifically set so that the former is approximately four times greater in value than the latter.
While provision of the clamp circuit results in a decrease in capacitance of the sense line SN, a capacitive balance between sense line SN and reference sense line RSN also affects the resulting sensing speed or rate. More specifically as has been explained in conjunction with FIG. 33, the voltage swing width of sense line SN is about four times greater than that of data line DL. In addition, sense line SN is about ten times less in capacitance than data line DL, wherein approximately 30 percent (%) or more or less of the amount of electrical charge to be charged when looking at from the load 102 is reserved for charge-up of the capacitor of sense line SN. Due to this, unless sense line SN and reference sense line RSN are precisely equalized in capacitance to each other, a difference in chargeup rate between them can result in a delay of data sense operations. In other words, in order to perform the data sense at high speeds, it is important to establish a well-valanced capacitance relation between sense line SN and reference sense line RSN while at the same time establishing a capacitive valance between data line DL and reference data line RDL.
Another purpose of the clamp circuit 105 is to suppress a drain voltage being given via the data line DL to a bit line BL of a cell array during reading. During data reading, in order to detect or sense whether a current is present or absent, a read voltage of the positive polarity is given to the control gate of a memory cell from a word line WL while letting a positive drain voltage be given from bitline BL. This voltage relationship is the same as that during writing of data “0.” If the drain voltage is high in potential then little write-in phenomenon (soft write) occurs. To prevent this, it is required that the drain voltage is potentially lowered to an extent that the memory cell MC performs no pentode operations. It is the clamp circuit 105 that performs this task.
On the other hand, in order to achieve high-speed chargeup of the sense line SN, it is an effective way to enlarge the transistor size (channel width) of the current-source load 102. Unfortunately this approach has a limit. This point will be discussed in detail below. See FIG. 34. This graph demonstrates the dependence of the chargeup time and sense line capacitance CSN on the transistor size of current-source load 102. While the size of a load transistor stays less, the load transistor capacitance is less dominant than both the wiring capacitance of sense line SN and the capacitance of remaining circuitry being connected to sense line SN, with the sense line capacitance CSN lessened in gradient. On the contrary, when the load transistor gets larger in size, the load transistor gate capacitance and junction capacitance become relatively larger, resulting in an increase in increment curve of sense line capacitance CSN. The time for sense-line charge is variable in a way which follows: while the load transistor stays less in size, it rapidly decreases with an increase in size; when the size becomes larger to a certain extent, a time taken to charge up itself becomes dominant in the sense delay, resulting in a decrease in gradient. As apparent from the foregoing, the scheme for enlarging the load transistor size in order to accelerate sense-line chargeup must come with a limit.
In recent years, most flash memories are designed to have a built-in page mode and/or burst mode as in traditional dynamic random access memory (DRAM) chips. Letting flash memories offer operabilities in these modes calls for the use of an increased number of on-chip sense amplifiers corresponding to one page of data—for example, the page consists of eight (8) words of data, equal to 128 data bits in total. However, with the current-sensing type sense amplifiers stated supra, a need is felt to additionally use a reference data line with more than one dummy data line capacitor large in capacitance value and in area. Obviously, placing multiple sense amplifiers on a chip would result in a likewise increase in chip area due to the presence of such dummy data line capacitors.
As shown in FIG. 32, an equalize circuit 106 is provided between the sense line SN and reference sense line RSN, which is rendered operative prior to execution of a data sense operation to electrically short between these lines SN and RSN and thus short between the data line DL and reference data line RDL to thereby set them at the same potential level. Here, the equalize circuit 106 is formed of an n-channel metal insulator semiconductor filed effect transistor (MISFET).
As shown in FIG. 36 the equalize circuit 106 is driven by an equalize signal EQL to turn on selectively, thereby electrically shorting between the sense line SN and reference sense line RSN. At this time, it should be required for achievement of high-speed sense operations to set a time width t1-t0 of the equalize signal EQL at an optimal value necessary for electrical shorting between sense line SN and reference sense line RSN. When equalize signal EQL potentially drops at Low or “L” level causing an equalize operation to be completed. After completion of the equalization, a difference in voltage potential between sense line SN and reference sense line RSN increases in a way conformity with a voltage differential between data line DL and reference data line RDL. When the differential voltage ΔV reaches a prespecified value, a sense output SAout is obtained.
If the time width of equalize signal EQL is too small, then any reliable equalization is no longer executable. This can cause read errors or, alternatively, cause a delay in the sense operation due to a necessity to reverse or invert the voltage differential between the sense line SN and reference sense line RSN in a data dependent way. If the time width of the equalize signal EQL is too large, then the sense operation can also be delayed.
In the prior flash memory discussed above, what is fully considered with respect to the equalize circuit 106 is the behavior of switching noises. As shown in FIG. 36, the MISFET making up the equalize circuit has a capacitance component C1 between its gate and source and also has a capacitance C2 between the gate and drain thereof. Due to the presence of such capacitances C1, C2, upon releasing of equalization, that is, when the equalize signal EQL changes in potential from High (“H”) level to “L” level as shown in FIG. 37, significant switching noises N1, N2 would be added or “superimposed” to the reference sense line RSN and sense line SN.